View TMC93LC46_257808.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TMC 93LC46/56/57/66/86
1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM FEATURES
s High speed operation: s Power-up inadvertant write protection s 1,000,000 Program/erase cycles s 100 year data retention s Commercial, industrial and automotive
- 93LC46/56/57/66 : 1MHz - 93LC86 : 3MHz
s Low power CMOS technology s 1.8 to 6.0 volt operation s Selectable x8 or x16 memory organization s Self-timed write cycle with auto-clear s Hardware and software write protection
temperature ranges
s Sequential read (except TMC93LC46) s Program enable (PE) pin (TMC93LC86 only)
DESCRIPTION
The 93LC46/56/57/66/86 are 1K/2K/2K/4K/16K-bit Serial EEPROM memory devices which are configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The 93LC46/56/ 57/66/86 are manufactured using TMC's advanced CMOS EEPROM floating gate technology. The devices are designed to endure 1,000,000 program/erase cycles and have a data retention of 100 years. The devices are available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
CS SK DI DO
1 2 3 4 8 7 6 5
SOIC Package (J,W) SOIC Package (S,V) SOIC Package (K,X)
1 2 3 4 8 7 6 5
TSSOP Package (U,Y)**
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC (PE*) ORG GND
VCC NC (PE*) VCC NC (PE*) CS ORG SK GND
ORG GND DO DI
CS SK DI DO
1 2 3 4
8 7 6 5
VCC
CS
NC (PE*) SK DI ORG DO GND
1 2 3 4
8 7 6 5
VCC
NC (PE*) ORG
GND
PIN FUNCTIONS
Pin Name CS SK DI DO VCC GND ORG NC PE* Function Chip Select Clock Input Serial Data Input Serial Data Output +1.8 to 6.0V Power Supply Ground Memory Organization No Connection Program Enable
BLOCK DIAGRAM
VCC GND
ORG
MEMORY ARRAY ORGANIZATION
ADDRESS DECODER
DATA REGISTER DI CS PE* MODE DECODE LOGIC OUTPUT BUFFER
Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization.
SK
CLOCK GENERATOR
DO
93LC46/56/57/66/86 F02
(c) 2002 by TMC
Doc. No. 1023, Rev. G
93LC46/56/57/66/86 ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55C to +125C Storage Temperature ........................ -65C to +150C Voltage on any Pin with Respect to Ground(1) ............. -2.0V to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (TA = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS
Symbol NEND(3) TDR(3) VZAP(3) ILTH
(3)(4)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
Min 1,000,000 100 2000 100
Typ
Max
Units Cycles/Byte Years Volts mA
D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol ICC1 ICC2 ISB1 ISB2(5) ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 5.0V CS = 0V ORG=GND CS=0V ORG=Float or VCC VIN = 0V to VCC VOUT = 0V to VCC, CS = 0V 4.5V VCC < 5.5V 4.5V VCC < 5.5V 1.8V VCC < 4.5V 4.8V VCC < 4.5V 4.5V VCC < 5.5V IOL = 2.1mA 4.5V VCC < 5.5V IOH = -400A 1.8V VCC < 4.5V IOL = 1mA 1.8V VCC < 4.5V IOH = -100A VCC - 0.2 2.4 0.2 -0.1 2 0 VCC x 0.7 Min Typ Max 3 500 10 0 1 1 0.8 VCC + 1 VCC x 0.2 VCC+1 0.4 Units mA A A A A A V V V V V V V V
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. (5) Standby Current (ISB2)=0A (<900nA) for 93LC46/56/57/66, (ISB2)=2A for 93LC86.
Doc. No. 1023, Rev. G
2
93LC46/56/57/66/86
PIN CAPACITANCE Symbol COUT
(3)
Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG)
Conditions VOUT=0V VIN=0V
Min
Typ
Max 5 5
Units pF pF
CIN(3)
INSTRUCTION SET Instruction Device Type READ Start Opcode Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 10 10 10 10 11 11 11 11 11 01 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Address x8 x16 A6-A0 A8-A0 A8-A0 A7-A0 A10-A0 A6-A0 A8-A0 A8-A0 A7-A0 A10-A0 A6-A0 A8-A0 A8-A0 A7-A0 A10-A0 A5-A0 A7-A0 A7-A0 A6-A0 A9-A0 A5-A0 A7-A0 A7-A0 A6-A0 A9-A0 A5-A0 A7-A0 A7-A0 A6-A0 A9-A0 D7-D0 D7-D0 D7-D0 D7-D0 D7-D0 D15-D0 D15-D0 D15-D0 D15-D0 D15-D0 Data x8 x16 Comments Read Address AN-A0 PE(2)
93LC46 93LC56(1) 93LC66 93LC57 93LC86 93LC46 93LC56(1) 93LC66 93LC57 93LC86 93LC46 93LC56(1) 93LC66 93LC57 93LC86 93LC46 93LC56 93LC66 93LC57 93LC86 93LC46 93LC56 93LC66 93LC57 93LC86 93LC46 93LC56 93LC66 93LC57 93LC86 93LC46 93LC56 93LC66 93LC57 93LC86
X Clear Address AN-A0
ERASE
I Write Address AN-A0
WRITE
I Write Enable
EWEN
11XXXXX 11XXXX 11XXXXXXX 11XXXXXX 11XXXXXXX 11XXXXXX 11XXXXXX 11XXXXX 11XXXXXXXXX 11XXXXXXXX 00XXXXX 00XXXX 00XXXXXXX 00XXXXXX 00XXXXXXX 00XXXXXX 00XXXXXX 00XXXXX 00XXXXXXXXX 00XXXXXXXX 10XXXXX 10XXXX 10XXXXXXX 10XXXXXX 10XXXXXXX 10XXXXXX 10XXXXXX 10XXXXX 10XXXXXXXXX 10XXXXXXXX 01XXXXX 01XXXX 01XXXXXXX 01XXXXXX 01XXXXXXX 01XXXXXX 01XXXXXX 01XXXXX 01XXXXXXXXX 01XXXXXXXX
X Write Disable
EWDS
X Clear All Addresses
ERAL
I D7-D0 D7-D0 D7-D0 D7-D0 D7-D0 D15-D0 D15-D0 D15-D0 D15-D0 D15-D0 Write All Addresses
WRAL
I
Note: (1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and ERASE commands. (2) Applicable only to 93LC86 (3) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 1023, Rev. G
93LC46/56/57/66/86
A.C. CHARACTERISTICS (93LC46/56/57/66) Limits VCC = 1.8V-6V Test SYMBOL PARAMETER tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 1 1 1 1 250 DC CL = 100pF (3) Conditions Min 200 0 400 400 1 1 400 10 0.5 0.5 0.5 0.5 500 DC Max Min 100 0 200 200 0.5 0.5 200 10 0.25 0.25 0.25 0.25 1000 Max Min 50 0 100 100 0.25 0.25 100 10 Max Units ns ns ns ns s s ns ms s s s s kHz VCC = 2.5V-6V VCC = 4.5V-5.5V
A.C. CHARACTERISTICS (93LC86) Limits Test SYMBOL PARAMETER tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 1 1 1 1 500 DC CL = 100pF (3) Conditions VCC = 1.8V-6V Min 200 0 200 200 1 1 400 5 0.5 0.5 0.5 0.5 1000 DC Max VCC = 2.5V-6V Min 100 0 100 100 0.5 0.5 200 5 0.15 0.15 0.15 0.1 3000 Max VCC = 4.5V-5.5V Min 50 0 50 50 0.15 0.15 100 5 Max Units ns ns ns ns s s ns ms s s s s kHz
NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1023, Rev. G
4
93LC46/56/57/66/86
POWER-UP TIMING (1)(2) SYMBOL tPUR tPUW PARAMETER Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms
NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) The input levels and timing reference points are shown in "AC Test Conditions" table.
A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages 50ns 0.4V to 2.4V 0.8V, 2.0V 0.2VCC to 0.7VCC 0.5VCC 4.5V VCC 5.5V 4.5V VCC 5.5V 1.8V VCC 4.5V 1.8V VCC 4.5V
5
Doc. No. 1023, Rev. G
93LC46/56/57/66/86 DEVICE OPERATION
The 93LC46/56(57)66/86 is a 1024/2048/4096/ 16,384-bit nonvolatile memory intended for use with industry standard microprocessors. The 93LC46/56/ 57/66/86 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9-bit instructions for 93LC46;seven 10-bit instructions for 93LC57; seven 11-bit instructions for 93LC56 and 93LC66;seven 13-bit instructions for 93LC86; control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions for 93LC46; seven 11-bit instructions for 93LC57; seven 12-bit instructions for 93LC56 and 93LC66:seven 14-bit instructions for 93LC86; control the reading, writing and erase operations of the device. The 93LC46/56/57/66/86 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy "1" into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin.
Figure 1. Sychronous Data Timing
tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID
93LC46/56/57/66/86 F03
tSKLOW
tCSH
tDIH VALID
VALID
tCSMIN
Figure 2a. Read Instruction Timing (93LC46)
SK tCSMIN CS STANDBY AN DI 1 1 0 tHZ 0 DN DN-- 1 D1 D0
93LC46/56/57/66/86 F04
AN--1
A0
DO
HIGH-Z
tPD0
HIGH-Z
Doc. No. 1023, Rev. G
6
93LC46/56/57/66/86
increment to the next address and shift out the next data The format for all instructions sent to the device is a word in a sequential READ mode. As long as CS is logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93LC46)/ /7-bit (93LC57)/ 8-bit (93LC56 or 93LC66)/10-bit (93LC86) continuously asserted and SK continues to toggle, the device will keep incrementing to the next address (an additional bit when organized X8) and for write automatically until it reaches to the end of the address operations a 16-bit data field (8-bit for X8 organizations). space, then loops back to address 0. In the sequential Note: This note is applicable only to 93LC86. The Write, READ mode, only the initial data word is preceeded by Erase, Write all and Erase all instructions require PE=1. a dummy zero bit. All subsequent data words will follow If PE is left floating, 93C86 is in Program Enabled mode. without a dummy zero bit. For Write Enable and Write Disable instruction PE=don't Write care. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the 93LC46/ 56/57/66/86 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the 93LC56/57/66/86, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically Figure 2b. Read Instruction Timing (93LC56/57/66/86)
SK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the 93LC46/56/57/66/86 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into.
CS Don't Care AN DI 1 1 0 AN-1 A0
DO
HIGH-Z
Dummy 0
D15 . . . D0 or D7 . . . D0
Address + 1 D15 . . . D0 or D7 . . . D0
Address + 2 D15 . . . D0 or D7 . . . D0
Address + n D15 . . . or D7 . . .
Figure 3. Write Instruction Timing
SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW
93LC46/56/57/66/86 F05
STATUS VERIFY AN-1 A0 DN D0
STANDBY
BUSY READY
tHZ HIGH-Z
7
Doc. No. 1023, Rev. G
93LC46/56/57/66/86
Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the 93LC46/56/57/66/86 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state. Erase/Write Enable and Disable The 93LC46/56/57/66/86 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all 93LC46/56/57/66/86 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the 93LC46/56/57/66/86 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical "1" state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. (Note 1.) The ready/ busy status of the 93LC46/56/57/66/86 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.
Figure 4. Erase Instruction Timing
SK
CS AN DI 1 1 1 tSV HIGH-Z DO AN-1 A0
STATUS VERIFY tCS
STANDBY
tHZ BUSY tEW READY HIGH-Z
93LC46/56/57/66/86 F06
Doc. No. 1023, Rev. G
8
93LC46/56/57/66/86
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
* * ENABLE=11 DISABLE=00
93LC46/56/57/66/86 F07
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY tCS
STANDBY
DI
1
0
0
1
0 tSV tHZ BUSY tEW READY HIGH-Z
DO
HIGH-Z
93LC46/56/57/66/86 F08
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY tCSMIN
STANDBY
DI
1
0
0
0
1
DN
D0 tSV tHZ BUSY tEW READY HIGH-Z
DO
93LC46/56/57/66/86 F09
9
Doc. No. 1023, Rev. G
Package Information
Plastic DIP Outline Dimensions
8-pin DIP (300mil) Outline Dimensions
A B 1 8 5 4
H C D E . G
=
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 355 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 375 260 135 145 20 70 3/4 315 375 15
Package Information
SOP Outline Dimensions
8-pin SOP (150mil) Outline Dimensions
A 1
8
5 B 4
C
C' G D E .
H
=
Symbol A B C C D E F G H a
Dimensions in mil Min. 228 149 14 189 53 3/4 4 22 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 244 157 20 197 69 3/4 10 28 12 10
Package Information
Carrier Tape Dimensions
D
E .
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 8N Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 12.0+0.3 -0.1 8.00.1 1.750.1 5.50.1 1.550.1 1.5+0.25 4.00.1 2.00.1 6.40.1 5.200.1 2.10.1 0.30.05 9.3

▲Up To Search▲

Price & Availability of TMC93LC46

	To Download TMC93LC46 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .